Review: VIA Cyrix III / Samuel

Details on the Cyrix III

VIAs Cyrix III is the first non-Intel CPU designed for the P6 bus. This means that the Celeron will have a competitor fighting for its socket. Due to patent issues, other manufacturers have not been permitted to produce P6 clones so far. VIA works around this problem just as with their chipsets, i.e. the company signed cross-licensing agreements with National Semiconductors, who also produce some of the CPUs. National in turn has entered into comprehensive cross-licensing agreements with Intel and is therefore allowed to use the protocol of the P6 bus. National, moreover, was the previous owner of Cyrix before VIA acquired the chip maker.

Originally Cyrix III was designed to include the Joshua core, which was based on the Cyrix M2 technology. Key features included a 64-KByte L1 cache, an 256-KByte L2 cache and two pipelines for the FPU und MMX units. The FSB was designed to be clocked at 133 MHz.

Quite a number of changes have been made in this respect on the final Cyrix III with the core of the WinChip-C5A (aka Samuel). The CPU now has an L1 cache with a total of 128 KBytes. The design, which is based on the Winchip 4 (Socket 7), splits this L1 cache into two 64 KBytes sections for instructions and data. But the CPU socket is not the only difference between the Cyrix III and the WinChip 4. However, VIA has not disclosed many details on the architecture of the Cyrix III. The company only stated that Cyrix III had a 12-stage pipeline. The WinChip-4 came with only 8 stages for its pipeline.

Beefed up: The core of the VIA Cyrix III is based on the architecture of the WinChip-4 by IDT.
Beefed up: The core of the VIA Cyrix III is based on the architecture of the WinChip-4 by IDT.

Our analysis revealed another difference. Both parts of the L1 cache only work with 4-way associativity. This was originally planned by IDT for the data cache only. Much like the WinChip-4, the TLBs (translation look-up buffers) of the Cyrix III can hold 128 entries and work with 8-way associativity. Please refer to our feature on Processor Basics in the Cache Basics section for detailed information on associative caches. The feature is currently only available in German - please bear with us.

In general, the IDT team led by designer Glenn Henry keeps to their basic concept: a highly integrated core and a simple architecture make for a small die. Leaving out the L2 cache completely is unusual, though. This must be the tribute paid for the low price of the CPU. Only the successor to the current Cyrix III (code name: Samuel 2) will have a 64 KB L2 cache.