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At the Computex trade show in Taiwan from June 5 to June 9, the VIA stand was bustling with people. Much to everyone's surprise, the company announced on the second day of the show that it would ship the Cyrix III with a new core. This announcement confirmed what was rumored before: the CPU developed under the code name "Joshua", which had been delayed several times, was finally cancelled due to lack of performance. VIA stated that they would launch their first CPU featuring the Samuel core, originally developed by IDT. In summer 1999 VIA had acquired IDT. The IDT team, now working for VIA, was three months ahead of its schedule. VIA therefore decided to give up the Joshua core the Cyrix team was working on. However, VIA kept the name of "Cyrix III" in order to avoid wasting the money the company had already spent on the marketing campaign. But from a technical point of view, the "Cyrix III" has nothing to do with Cyrix anymore.
The Cyrix III fits into the Socket 370 and is claimed to be fully compatible with the Celeron in its PGA packaged version. The new CPU targets the cut-price market and will initially be available at clock speeds of 500 and 533 MHz, with the FSB clocked at either 100 or 133 MHz. It also features AMD's 3DNow! instruction set and MMX. The cache design of the Cyrix III is rather unusual: while it does have two 64 KByte L1 caches for instructions and data, it lacks an L2 cache.