Low power dissipation
Despite the lack of an L2 cache, VIA's Dynamic Power Caching Architecture is designed to ensure an optimum balance between high performance and low power dissipation. This marketing jargon describes a simple idea: sacrificing the L2 cache reduces the number of transistors and total power consumption. At 10.5 W max under heavy load and 2 W when idle (both figures apply to the 533 MHz version), the Cyrix III is a rather modest CPU. The core voltage is specified at 1.9 V. These figures make VIA's CPUs an interesting option for notebooks, too. VIA intends to offer special versions of the processor under the name of "Cyrix III LP" with PGA and BGA packaging for mobile computers soon. Here as well, VIA plans to ensure full compatibility with the Celeron for easy implementation in existing machine designs.
One reason for the low power consumption of the Cyrix III is the advanced 0.18 micron manufacturing technology. The Cyrix III is therefore able to hold 11.2 million transistors in one die of only 72 square millimeters in size. This die is made of six metal layers. To put these numbers into perspective: the Celeron 566 at 0.18 micron has a die of 104 square millimeters, which holds 9.5 million transistors for the core and the L1 cache plus an additional 9.3 million transistors for the integrated L2 cache.
In addition to its MMX instructions, the Cyrix III also features the 3DNow! instruction set by AMD. The processor runs its FSB at either 100 MHz (Cyrix III 500) or 133 MHz (Cyrix III 533). VIA intends to ship the Cyrix III with a locked multiplier, which leaves little scope for overclocking.
With the new CPU VIA does not continue its tradition of "PR rating" a processor, which did not specify the exact clock speed but the performance in comparison to an Intel chip at the PR rated clock speed. For the Cyrix III, the given clock speed spells real megahertz.