Review: AMD Duron

Cache Architecture

The external L2 cache of the previous Athlon models only worked with 2-way associativity but in turn was 512 KByte in size. With the Thunderbird, AMD launched an L2 cache working with 8-way associativity. The Duron with its 64-Kbyte L2 cache adopted the design approach pursued for the latter.

Please refer to our feature on Processor Basics in the Cache Basics section for detailed information on associative caches. The feature is currently only available in German - please bear with us.

However, AMD has not made any changes on the L1 cache. The Duron's L1 cache continues to work with 2-way associativity and to be 128 KBytes in size, i.e. 64 KBytes each for instructions and data.