Multiprocessing: Functions and Features

Cache Consistency through MESI

All processors of a SMP system can access the shared main memory. Exclusive resources such as local processor cache can lead to problems. If data are located in a certain memory area of processor 0, the CPU will use its fast cache when the data are accessed again. This however can lead to inconsistencies, if processor 1 has overwritten this memory area in the meantime with new data.

For this reason SMP systems feature a cache coherence protocol. It ensures permanently consistent data in the main memory and the cache of the processor. A widely distributed protocol for multiprocessors is MESI (modified, exclusive, shared and invalid). Each cache line can represent one of the four different conditions:

• Modified: The cache line exists in only one processor and contains modified data. The data does not match the data in the main memory anymore.

• Exclusive: The cache line is only saved in one processor. However, the data are not modified and match the related area in the main memory.

• Shared: A cache line exists in multiple processors. Write commands are now done through a write-through to the main memory. Through this event the cache lines in all other processors become invalid.

• Invalid: The content of the cache line is invalid. A read access to an invalid cache creates a cache miss. The processor fetches data in this case from the main memory.