VIA Chipsets slow down PCI cards

PCI Latency Patch

It was not VIA, but independent programmer George Breese of Networking Resources from New York who first came up with a patch for some of VIAs problems with the PCI bus. George often posts in the independent forums at VIAHardware, who also offer the patch as a direct download.

Please note: This is not an "official" patch supplied by VIA or any motherboard manufacturer. You may use it at your own risk. To date, we could not verify if there are any stability issues implied through longer burst cycles. However, we did not see any crashes or incompatibilities after applying this patch. But, taking its severe modifications into account, this is not completely impossible. You should read the files included in the download before going any further.

The patch deals with PCI Latency, among other things. This PCI Latency sets the number of cycles, that one PCI-Busmaster-Device can request the bus for exclusive use, before releasing it. This minimum amount of clock cycles is set, so PCI performance will not decrease too much, if burst transfers are interrupted too often. On the other hand, the latency timer also prevents one device from making exclusive use of the bus for too long. After the PCI latency during one burst has passed, every other device can request usage of the bus. The burst is then cancelled immediately.

The PCI-Latency-Patch with Version 0.19 mainly changes the following settings by setting registers in the northbridge:

  • Turns off options "PCI Delay Transaction" and "PCI Master Read Caching" (Registers 70, Bit 1 and 2).

  • Sets Arbitration-Timer of the PCI-Controller to 96 clock cycles. One typical BIOS-default is 32 clocks. This new setting is made to work around the older IDE bug in VIAs 686B southbridge (Register 75, Bit 0-2 or 0-3, depending on chipset).

  • The VIA PCI controller's "PCI Latency" timer, which is normally used to guarantee the CPU at least a specified number of PCI clock cycles when accessing the PCI bus, is set to zero. (Register 0D)

  • The CPU is removed from PCI priority rotation. Ordinarily, the CPU can be guaranteed access to the PCI bus after one to three other devices have used the bus. (Register 76, bits 4 and 5, and bit 7 on older chipsets).

We did a quick cross check with this patch using the Promise Ultra133 TX2 and a few motherboards. It all resulted in better burst transfers.

Burst transfers

Chipset

No Latency-Patch

With Latency-Patch

Promise Ultra133 TX2 and Maxtor DiamondMax D740X

VIA MVP3

63,5 MBytes/s

84,1 MBytes/s

VIA KT133A

78,2 MBytes/s

93,4 MBytes/s

VIA P4X266A

90,1 MBytes/s

100,9 MBytes/s

As burst transfers are still not en par with Intel chips they still are 32 per cent higher now than without the patch.

Pain relief: Burst transfers now include 32 packets of data.
Pain relief: Burst transfers now include 32 packets of data.

Checking the PCI timing with the logic analyzer we found that now bursts with VIA chipsets transferred 32 packets of data. Only then the bus is released. Without the patch, this was only 24 packets of data. These longer bursts explain the increase in performance.

Playing around with the patch a little more we found that even audio applications can gain a great benefit from it. One system with a professional DSP sound card for studio use lost all the drops of notes it showed before. Without the patch, one single note played by a software sampler was audibly interrupted frequently. This effect disappeared after applying the patch. It's another indication, that PCI transfers got interrupted to often.